 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| VS1103B VS1103B VS1103B - MIDI/ADPCM AUDIO CODEC Features * Mixes three audio sources - General MIDI 1+ / SP-MIDI - WAV (PCM + IMA ADPCM) - Microphone or line input * Encodes IMA ADPCM from microphone, line input or mixed output * Input streams can use different sample rates * EarSpeaker Spatial Processing * Bass and treble controls * Operates with a single 12. . . 13 MHz clock * Internal PLL clock multiplier * Low-power operation * High-quality on-chip stereo DAC with no phase error between channels * Stereo earphone driver capable of driving a 30 load * Separate operating voltages for analog, digital and I/O * 5.5 KiB On-chip RAM for user code / data * Serial control and data interfaces * Can be used as a slave co-processor * SPI flash boot for special applications * UART for debugging purposes * New functions may be added with software and 4 GPIO pins Description VS1103B is a single-chip MIDI/ADPCM/WAV audio decoder and ADPCM encoder that can handle upto three simultaneous audio streams. It can also act as a Midi synthesizer. VS1103B contains a high-performance, proprietary low-power DSP processor core VS DSP4 , working data memory, 5 KiB instruction RAM and 0.5 KiB data RAM for user applications, serial control and input data interfaces, 4 general purpose I/O pins, an UART, as well as a high-quality variable-sample-rate mono ADC and stereo DAC, followed by an earphone amplifier and a common buffer. VS1103B receives its input bitstreams through serial input buses, which it listens to as a system slave. The input streams are decoded and passed through digital volume controls to an 18-bit oversampling, multi-bit, sigma-delta DAC. Decoding is controlled via a serial control bus. In addition to basic decoding, it is possible to add application specific features, like DSP effects, to user RAM memory. mic audio line audio GPIO VS1103 MIC AMP 4 GPIO MUX Mono ADC Stereo DAC Stereo Ear- phone Driver audio L R output X ROM DREQ SO SI SCLK XCS XDCS Serial Data/ Control Interface X RAM VSDSP 4 Y ROM RX TX UART Y RAM Clock multiplier Instruction RAM Instruction ROM Version 1.01, 2007-09-03 1 VLSI Solution y VS1103B VS1103B CONTENTS Contents 1 2 3 Disclaimer Definitions Characteristics & Specifications 3.1 3.2 3.3 3.4 3.5 3.6 4 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . Analog Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Digital Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Switching Characteristics - Boot Initialization . . . . . . . . . . . . . . . . . . . . . . . 8 8 9 9 9 10 11 11 11 12 12 12 12 13 15 15 15 15 15 16 16 Packages and Pin Descriptions 4.1 Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1.1 4.1.2 4.2 LQFP-48 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . BGA-49 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . LQFP-48 and BGA-49 Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . 5 SPI Buses 5.1 5.2 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SPI Bus Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.2.1 5.2.2 5.3 5.4 VS1002 Native Modes (New Mode) . . . . . . . . . . . . . . . . . . . . . . . . VS1001 Compatibility Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data Request Pin DREQ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Serial Protocol for Serial Data Interface (SDI) . . . . . . . . . . . . . . . . . . . . . . . Version 1.01, 2007-09-03 2 VLSI Solution y VS1103B 5.4.1 5.4.2 5.4.3 5.4.4 VS1103B CONTENTS General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SDI in VS1002 Native Modes (Recommended) . . . . . . . . . . . . . . . . . . SDI in VS1001 Compatibility Mode . . . . . . . . . . . . . . . . . . . . . . . . Passive SDI Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 16 17 17 17 17 18 18 19 20 21 21 21 22 23 23 23 23 24 26 26 27 28 28 5.5 Serial Protocol for Serial Command Interface (SCI) . . . . . . . . . . . . . . . . . . . . 5.5.1 5.5.2 5.5.3 5.5.4 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SCI Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SCI Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SCI Multiple Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.6 5.7 SPI Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SPI Examples with SM SDINEW and SM SDISHARED set . . . . . . . . . . . . . . . 5.7.1 5.7.2 5.7.3 Two SCI Writes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Two SDI Bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SCI Operation in Middle of Two SDI Bytes . . . . . . . . . . . . . . . . . . . . 6 Functional Description 6.1 6.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Supported Audio Codecs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.2.1 6.2.2 6.3 Supported RIFF WAV Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . Supported MIDI Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data Flow of VS1103B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.3.1 6.3.2 Normal Data Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Real-Time RT-Midi Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.4 6.5 Serial Data Interface (SDI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Serial Control Interface (SCI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Version 1.01, 2007-09-03 3 VLSI Solution y VS1103B VS1103B CONTENTS 6.6 SCI Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.6.1 6.6.2 6.6.3 6.6.4 6.6.5 6.6.6 6.6.7 6.6.8 6.6.9 SCI MODE (RW) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SCI STATUS (RW) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SCI BASS (RW) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SCI CLOCKF (RW) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SCI DECODE TIME (RW) . . . . . . . . . . . . . . . . . . . . . . . . . . . . SCI AUDATA (RW) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SCI WRAM (RW) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SCI WRAMADDR (W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SCI IN0 and SCI IN1 (R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 29 31 31 32 33 33 33 33 34 34 34 35 35 36 37 37 37 37 38 38 38 39 40 6.6.10 SCI AIADDR (RW) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.6.11 SCI VOL (RW) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.6.12 SCI MIXERVOL (RW) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.6.13 SCI ADPCMRECCTL (RW) . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.6.14 SCI AICTRL[x] (RW) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Operation 7.1 7.2 7.3 7.4 Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Hardware Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Software Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ADPCM Recording . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.4.1 7.4.2 7.4.3 7.4.4 Activating ADPCM Recording . . . . . . . . . . . . . . . . . . . . . . . . . . . Reading IMA ADPCM Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . Adding a RIFF Header . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Playing ADPCM Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Version 1.01, 2007-09-03 4 VLSI Solution y VS1103B 7.4.5 7.4.6 VS1103B CONTENTS Sample Rate Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . Example Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 40 42 42 42 42 43 43 44 44 45 45 45 45 45 45 46 47 48 49 50 50 51 51 7.5 7.6 7.7 7.8 SPI Boot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Play/Decode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Feeding PCM data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SDI Tests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.8.1 7.8.2 7.8.3 7.8.4 Sine Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Memory Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SCI Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 VS1103B Registers 8.1 8.2 8.3 8.4 8.5 8.6 8.7 8.8 8.9 Who Needs to Read This Chapter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . The Processor Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VS1103B Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SCI Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Serial Data Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DAC Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GPIO Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interrupt Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A/D Modulator Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.10 Watchdog v1.0 2002-08-26 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.10.1 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.11 UART v1.0 2002-04-23 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.11.1 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Version 1.01, 2007-09-03 5 VLSI Solution y VS1103B VS1103B CONTENTS 8.11.2 Status UARTx STATUS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.11.3 Data UARTx DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.11.4 Data High UARTx DATAH . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.11.5 Divider UARTx DIV . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.11.6 Interrupts and Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.12 Timers v1.0 2002-04-23 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.12.1 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.12.2 Configuration TIMER CONFIG . . . . . . . . . . . . . . . . . . . . . . . . . . 8.12.3 Configuration TIMER ENABLE . . . . . . . . . . . . . . . . . . . . . . . . . . 8.12.4 Timer X Startvalue TIMER Tx[L/H] . . . . . . . . . . . . . . . . . . . . . . . 8.12.5 Timer X Counter TIMER TxCNT[L/H] . . . . . . . . . . . . . . . . . . . . . . 8.12.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.13 System Vector Tags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.13.1 AudioInt, 0x20 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.13.2 SciInt, 0x21 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.13.3 DataInt, 0x22 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.13.4 ModuInt, 0x23 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.13.5 TxInt, 0x24 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.13.6 RxInt, 0x25 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.13.7 Timer0Int, 0x26 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.13.8 Timer1Int, 0x27 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.13.9 UserCodec, 0x0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.14 System Vector Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.14.1 WriteIRam(), 0x2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 52 52 52 53 54 54 54 55 55 55 55 56 56 56 56 56 57 57 57 57 58 58 58 Version 1.01, 2007-09-03 6 VLSI Solution y VS1103B VS1103B LIST OF FIGURES 8.14.2 ReadIRam(), 0x4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.14.3 DataBytes(), 0x6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.14.4 GetDataByte(), 0x8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.14.5 GetDataWords(), 0xa . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.14.6 Reboot(), 0xc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Document Version Changes 58 58 59 59 59 60 61 10 Contact Information List of Figures 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Pin Configuration, LQFP-48. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Configuration, BGA-49. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . BSYNC Signal - one byte transfer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . BSYNC Signal - two byte transfer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SCI Word Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SCI Word Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SCI Multiple Word Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SPI Timing Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Two SCI Operations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Two SDI Bytes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Two SDI Bytes Separated By an SCI Operation. . . . . . . . . . . . . . . . . . . . . . . Normal Data Flow of VS1103B, Part 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . Normal Data Flow of VS1103B, Part 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . User's Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RS232 Serial Interface Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 12 17 17 18 18 19 20 21 21 22 26 27 46 51 Version 1.01, 2007-09-03 7 VLSI Solution y VS1103B VS1103B 1. DISCLAIMER 1 Disclaimer All properties and figures are subject to change. 2 Definitions B Byte, 8 bits. b Bit. Ki "Kibi" = 210 = 1024 (IEC 60027-2). Mi "Mebi" = 220 = 1048576 (IEC 60027-2). VS DSP VLSI Solution's DSP core. W Word. In VS DSP, instruction words are 32-bit and data words are 16-bit wide. Version 1.01, 2007-09-03 8 VLSI Solution y VS1103B3. CHARACTERISTICS & SPECIFICATIONS VS1103B 3 3.1 Characteristics & Specifications Absolute Maximum Ratings Symbol AVDD CVDD IOVDD Min -0.3 -0.3 -0.3 -0.3 -40 -65 Max 2.85 2.7 3.6 50 IOVDD+0.31 +85 +150 Unit V V V mA V C C Parameter Analog Positive Supply Digital Positive Supply I/O Positive Supply Current at Any Digital Output Voltage at Any Digital Input Operating Temperature Storage Temperature 1 Must not exceed 3.6 V 3.2 Recommended Operating Conditions Symbol AGND DGND AVDD CVDD IOVDD XTALI CLKI Min -40 2.6 2.4 CVDD-0.6V 12 12 1.0x 40 Typ 0.0 2.8 2.5 2.8 12.288 36.864 3.0x 50 Max +85 2.85 2.7 3.6 13 52.04 4.5x4 60 Unit C V V V V MHz MHz % Parameter Ambient Operating Temperature Analog and Digital Ground 1 Positive Analog Positive Digital I/O Voltage Input Clock Frequency2 Internal Clock Frequency Internal Clock Multiplier3 Master Clock Duty Cycle 1 2 Must be connected together as close the device as possible for latch-up immunity. The maximum sample rate that can be played with correct speed is XTALI/256. Thus, XTALI must be at least 12.288 MHz to be able to play 48 kHz at correct speed. For other implications rising from not using a 12.288 MHz clock, see Chapter 7.4.5. 3 Reset value is 1.0x. Recommended SC MULT=4.0x. Performance may be poor if SC MULT< 3.5. 4 52.0 MHz is the maximum clock for the full CVDD range. (4.0 x 12.288 MHz=49.152 MHz or 3.5 x 13.0 MHz=45.5 MHz) Version 1.01, 2007-09-03 9 VLSI Solution y VS1103B3. CHARACTERISTICS & SPECIFICATIONS VS1103B 3.3 Analog Characteristics Unless otherwise noted: AVDD=2.5..2.85V, CVDD=2.4..2.7V, IOVDD=CVDD-0.6V..3.6V, TA=-25..+70 C, XTALI=12..13MHz, Internal Clock Multiplier 3.5x. DAC tested with 1307.894 Hz full-scale output sinewave, measurement bandwidth 20..20000 Hz, analog output load: LEFT to GBUF 30, RIGHT to GBUF 30. Microphone test amplitude 50 mVpp, fs =1 kHz, Line input test amplitude 1.1 V, fs =1 kHz. Parameter DAC Resolution Total Harmonic Distortion Dynamic Range (DAC unmuted, A-weighted) S/N Ratio (full scale signal) Interchannel Isolation (Cross Talk) Interchannel Isolation (Cross Talk), with GBUF Interchannel Gain Mismatch Frequency Response Full Scale Output Voltage (Peak-to-peak) Deviation from Linear Phase Analog Output Load Resistance Analog Output Load Capacitance Microphone input amplifier gain Microphone input amplitude Microphone Total Harmonic Distortion Microphone S/N Ratio Line input amplitude Line input Total Harmonic Distortion Line input S/N Ratio Line and Microphone input impedances 1 2 Symbol THD IDR SNR Min Typ 18 0.1 90 75 40 Max 0.3 70 50 -0.5 -0.1 1.3 1.51 302 0.5 0.1 1.7 5 100 Unit bits % dB dB dB dB dB dB Vpp AOLR MICG MTHD MSNR LTHD LSNR 16 50 60 26 50 0.02 62 2200 0.06 68 100 1403 0.10 28003 0.10 pF dB mVpp AC % dB mVpp AC % dB k 3.0 volts can be achieved with +-to-+ wiring for mono difference sound. AOLR may be much lower, but below Typical distortion performance may be compromised. 3 Harmonic Distortion increases above typical amplitude. Version 1.01, 2007-09-03 10 VLSI Solution y VS1103B3. CHARACTERISTICS & SPECIFICATIONS VS1103B 3.4 TBD Power Consumption 3.5 Digital Characteristics Symbol Min 0.7xIOVDD -0.2 0.7xIOVDD -1.0 Typ Max IOVDD+0.31 0.3xIOVDD 0.3xIOVDD 1.0 CLKI 6 Parameter High-Level Input Voltage Low-Level Input Voltage High-Level Output Voltage at IO = -1.0 mA Low-Level Output Voltage at IO = 1.0 mA Input Leakage Current SPI Input Clock Frequency 2 Rise time of all output pins, load = 50 pF 1 2 50 Unit V V V V A MHz ns Must not exceed 3.6V Value for SCI reads. SCI and SDI writes allow CLKI 4. 3.6 Switching Characteristics - Boot Initialization Parameter XRESET active time XRESET inactive to software ready Power on reset, rise time to CVDD 1 Symbol Min 2 16600 10 Max 500001 Unit XTALI XTALI V/s DREQ rises when initialization is complete. You should not send any data or commands before that. Version 1.01, 2007-09-03 11 VLSI Solution y VS1103B VS1103B 4. PACKAGES AND PIN DESCRIPTIONS 4 4.1 Packages and Pin Descriptions Packages Both LPQFP-48 and BGA-49 are lead (Pb) free and also RoHS compliant packages. RoHS is a short name of Directive 2002/95/EC on the restriction of the use of certain hazardous substances in electrical and electronic equipment. 4.1.1 LQFP-48 48 1 Figure 1: Pin Configuration, LQFP-48. LQFP-48 package dimensions are at http://www.vlsi.fi/ . 4.1.2 BGA-49 A1 BALL PAD CORNER 1 2 3 4 5 6 7 A B 4.80 7.00 C D E F G 0.80 TYP 0.80 TYP 4.80 7.00 1.10 REF TOP VIEW Figure 2: Pin Configuration, BGA-49. BGA-49 package dimensions are at http://www.vlsi.fi/ . 1.10 REF Version 1.01, 2007-09-03 12 VLSI Solution y VS1103B VS1103B 4. PACKAGES AND PIN DESCRIPTIONS 4.2 LQFP-48 and BGA-49 Pin Descriptions LQFP48 Pin 1 2 3 4 5 6 7 8 9 10 13 14 15 16 17 18 19 20 21 22 23 24 26 27 28 29 30 31 32 33 34 37 38 39 40 41 42 43 44 45 46 47 48 BGA49 Ball C3 C2 B1 D2 C1 D3 D1 E2 E1 F2 E3 F3 G2 F4 G3 E4 G4 F5 G5 F6 G6 G7 E6 F7 D6 E7 D5 D7 C6 C7 B6 C5 B5 A6 B4 A5 C4 A4 B3 A3 B2 A2 A1 Pin Type AI AI DI DGND CPWR IOPWR CPWR DO DIO DIO DI IOPWR DO DGND AO AI IOPWR IOPWR DGND DGND DGND DI CPWR DI DO DI DI DO3 CPWR DI DIO DIO APWR APWR AO APWR APWR AO APWR AIO APWR AO APWR AI Function Positive differential microphone input, self-biasing Negative differential microphone input, self-biasing Active low asynchronous reset Core & I/O ground Core power supply I/O power supply Core power supply Data request, input bus General purpose IO 2 / serial input data bus clock General purpose IO 3 / serial data input Data chip select / byte sync I/O power supply For testing only (Clock VCO output) Core & I/O ground Crystal output Crystal input I/O power supply I/O power supply Core & I/O ground Core & I/O ground Core & I/O ground Chip select input (active low) Core power supply UART receive, connect to IOVDD if not used UART transmit Clock for serial bus Serial input Serial output Core power supply Reserved for test, connect to IOVDD General purpose IO 0 / SPIBOOT, use 100 k pull-down resistor2 General purpose IO 1 Analog ground, low-noise reference Analog power supply Right channel output Analog ground Analog ground Common buffer for headphones Analog power supply Filtering capacitance for reference Analog power supply Left channel output Analog ground Line input Pin Name MICP MICN XRESET DGND0 CVDD0 IOVDD0 CVDD1 DREQ GPIO2 / DCLK1 GPIO3 / SDATA1 XDCS / BSYNC1 IOVDD1 VCO DGND1 XTALO XTALI IOVDD2 IOVDD3 DGND2 DGND3 DGND4 XCS CVDD2 RX TX SCLK SI SO CVDD3 TEST GPIO0 / SPIBOOT GPIO1 AGND0 AVDD0 RIGHT AGND1 AGND2 GBUF AVDD1 RCAP AVDD2 LEFT AGND3 LINEIN 1 2 First pin function is active in New Mode, latter in Compatibility Mode. Unless pull-down resistor is used, SPI Boot is tried. See Chapter 7.5 for details. Version 1.01, 2007-09-03 13 VLSI Solution y VS1103B VS1103B 4. PACKAGES AND PIN DESCRIPTIONS Pin types: Type DI DO DIO DO3 AI Description Digital input, CMOS Input Pad Digital output, CMOS Input Pad Digital input/output Digital output, CMOS Tri-stated Output Pad Analog input Type AO AIO APWR DGND CPWR IOPWR Description Analog output Analog input/output Analog power supply pin Core or I/O ground pin Core power supply pin I/O power supply pin In BGA-49, no-connect balls are A7, B7, D4, E5, F1, G1. In LQFP-48, no-connect pins are 11, 12, 25, 35, 36. Version 1.01, 2007-09-03 14 VLSI Solution y VS1103B VS1103B 5. SPI BUSES 5 5.1 SPI Buses General The SPI Bus - that was originally used in some Motorola devices - has been used for both VS1103B's Serial Data Interface SDI (Chapters 5.4 and 6.4) and Serial Control Interface SCI (Chapters 5.5 and 6.5). 5.2 5.2.1 SPI Bus Pin Descriptions VS1002 Native Modes (New Mode) These modes are active on VS1103B when SM SDINEW is set to 1 (default at startup). DCLK, SDATA and BSYNC are replaced with GPIO2, GPIO3 and XDCS, respectively. SDI Pin XDCS SCI Pin XCS Description Active low chip select input. A high level forces the serial interface into standby mode, ending the current operation. A high level also forces serial output (SO) to high impedance state. If SM SDISHARE is 1, pin XDCS is not used, but the signal is generated internally by inverting XCS. Serial clock input. The serial clock is also used internally as the master clock for the register interface. SCK can be gated or continuous. In either case, the first rising clock edge after XCS has gone low marks the first bit to be written. Serial input. If a chip select is active, SI is sampled on the rising CLK edge. Serial output. In reads, data is shifted out on the falling SCK edge. In writes SO is at a high impedance state. SCK SI SO 5.2.2 VS1001 Compatibility Mode This mode is active when SM SDINEW is set to 0. In this mode, DCLK, SDATA and BSYNC are active. SDI Pin SCI Pin XCS Description Active low chip select input. A high level forces the serial interface into standby mode, ending the current operation. A high level also forces serial output (SO) to high impedance state. SDI data is synchronized with a rising edge of BSYNC. Serial clock input. The serial clock is also used internally as the master clock for the register interface. SCK can be gated or continuous. In either case, the first rising clock edge after XCS has gone low marks the first bit to be written. Serial input. SI is sampled on the rising SCK edge, if XCS is low. Serial output. In reads, data is shifted out on the falling SCK edge. In writes SO is at a high impedance state. BSYNC DCLK SCK SDATA - SI SO Version 1.01, 2007-09-03 15 VLSI Solution y VS1103B VS1103B 5. SPI BUSES 5.3 Data Request Pin DREQ The DREQ pin/signal is used to signal if VS1103B's SDI FIFO is capable of receiving data. If DREQ is high, VS1103B can take at least 32 bytes of SDI data or one SCI command. Because of a 32-byte safety area, the sender may send upto 32 bytes of SDI data at a time without checking the status of DREQ, making controlling VS1103B easier for low-speed microcontrollers. If SARC DREQ512 is set, the safety area is 512 bytes (see Chapter 6.6.13). Note: DREQ may turn low or high at any time, even during a byte transmission. Thus, DREQ should only be used to decide whether to send more bytes. It should not abort a transmission that has already started. Note: In VS10XX products upto VS1002, DREQ was only used for SDI. In VS1103B DREQ is also used to tell the status of SCI. 5.4 5.4.1 Serial Protocol for Serial Data Interface (SDI) General The serial data interface operates in slave mode so the DCLK signal must be generated by an external circuit. Data (SDATA signal) can be clocked in at either the rising or falling edge of DCLK (Chapter 6.6). VS1103B assumes its data input to be byte-sychronized. SDI bytes may be transmitted either MSb or LSb first, depending of SCI MODE (Chapter 6.6.1). 5.4.2 SDI in VS1002 Native Modes (Recommended) In VS1002 native modes (SM NEWMODE is 1), byte synchronization is achieved by XDCS. The state of XDCS may not change while a data byte transfer is in progress. To always maintain data synchronization even if there may be glitches in the boards using VS1103B, it is recommended to turn XDCS every now and then, for instance once after every flash data block or a few kilobytes, just to keep sure the host and VS1103B are in sync. If SM SDISHARE is 1, the XDCS signal is internally generated by inverting the XCS input. For new designs, using VS1002 native modes are recommended. Version 1.01, 2007-09-03 16 VLSI Solution y VS1103B SDI in VS1001 Compatibility Mode BSYNC VS1103B 5. SPI BUSES 5.4.3 SDATA D7 D6 D5 D4 D3 D2 D1 D0 DCLK Figure 3: BSYNC Signal - one byte transfer. When VS1103B is running in VS1001 compatibility mode, a BSYNC signal must be generated to ensure correct bit-alignment of the input bitstream. The first DCLK sampling edge (rising or falling, depending on selected polarity), during which the BSYNC is high, marks the first bit of a byte (LSB, if LSB-first order is used, MSB, if MSB-first order is used). If BSYNC is '1' when the last bit is received, the receiver stays active and next 8 bits are also received. BSYNC SDATA D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 DCLK Figure 4: BSYNC Signal - two byte transfer. 5.4.4 Passive SDI Mode If SM NEWMODE is 0 and SM SDISHARE is 1, the operation is otherwise like the VS1001 compatibility mode, but bits are only received while the BSYNC signal is '1'. Rising edge of BSYNC is still used for synchronization. 5.5 Serial Protocol for Serial Command Interface (SCI) 5.5.1 General The serial bus protocol for the Serial Command Interface SCI (Chapter 6.5) consists of an instruction byte, address byte and one 16-bit data word. Each read or write operation can read or write a single register. Data bits are read at the rising edge, so the user should update data at the falling edge. Bytes are always sent MSb first. XCS should be low for the full duration of the operation, but you can have pauses between bits if needed. The operation is specified by an 8-bit instruction opcode. The supported instructions are read and write. See table below. Instruction Name Opcode Operation READ 0b0000 0011 Read data WRITE 0b0000 0010 Write data Note: VS1103B sets DREQ low after each SCI operation. The duration depends on the operation. It is not allowed to finish a new SCI/SDI operation before DREQ is high again. Version 1.01, 2007-09-03 17 VLSI Solution y VS1103B SCI Read XCS 0 SCK 3 SI 0 0 0 0 0 0 1 1 0 0 0 0 address 15 14 SO 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 1 0 don't care data out 1 0 X don't care 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 30 31 VS1103B 5. SPI BUSES 5.5.2 instruction (read) execution DREQ Figure 5: SCI Word Read VS1103B registers are read from using the following sequence, as shown in Figure 5. First, XCS line is pulled low to select the device. Then the READ opcode (0x3) is transmitted via the SI line followed by an 8-bit word address. After the address has been read in, any further data on SI is ignored by the chip. The 16-bit data corresponding to the received address will be shifted out onto the SO line. XCS should be driven high after data has been shifted out. DREQ is driven low for a short while when in a read operation by the chip. This is a very short time and doesn't require special user attention. 5.5.3 SCI Write XCS 0 SCK 3 SI 0 0 0 0 0 0 1 0 0 0 0 0 address 0 0 0 0 0 0 0 0 0 0 0 0 data out 0 0X 2 1 0 15 14 1 0 X 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 30 31 instruction (write) SO 0 0 0 0 0 0 execution DREQ Figure 6: SCI Word Write VS1103B registers are written from using the following sequence, as shown in Figure 6. First, XCS line is pulled low to select the device. Then the WRITE opcode (0x2) is transmitted via the SI line followed by an 8-bit word address. Version 1.01, 2007-09-03 18 VLSI Solution y VS1103B VS1103B 5. SPI BUSES After the word has been shifted in and the last clock has been sent, XCS should be pulled high to end the WRITE sequence. After the last bit has been sent, DREQ is driven low for the duration of the register update, marked "execution" in the figure. The time varies depending on the register and its contents (see table in Chapter 6.6 for details). If the maximum time is longer than what it takes from the microcontroller to feed the next SCI command or SDI byte, status of DREQ must be checked before finishing the next SCI/SDI operation. 5.5.4 SCI Multiple Write XCS 0 SCK 3 SI 0 0 0 0 0 0 1 0 0 0 0 0 address 0 0 0 0 0 0 0 0 0 0 0 data out 1 0 0 0 2 1 0 15 14 1 0 X data out 2 d.out n 0 0 0 0X 15 14 1 0 X 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 29 30 31 32 33 m-2m-1 instruction (write) SO 0 0 0 0 0 0 execution DREQ execution Figure 7: SCI Multiple Word Write VS1103B allows for the user to send multiple words to the same SCI register, which allows fast SCI uploads, shown in Figure 7. The main difference with a single write is that instead of bringing XCS up after sending the last bit of a data word, the next data word is sent immediately. After the last data word, XCS is driven high as with a single word write. After the last bit of a word has been sent, DREQ is driven low for the duration of the register update, marked "execution" in the figure. The time varies depending on the register and its contents (see table in Chapter 6.6 for details). If the maximum time is longer than what it takes from the microcontroller to feed the next SCI command or SDI byte, status of DREQ must be checked before finishing the next SCI/SDI operation. Version 1.01, 2007-09-03 19 VLSI Solution y VS1103B VS1103B 5. SPI BUSES 5.6 SPI Timing Diagram tXCSS tWL tWH tXCSH XCS 0 SCK 1 14 15 16 30 31 tXCS SI tH tSU SO tZ tV tDIS Figure 8: SPI Timing Diagram. Symbol tXCSS tSU tH tZ tWL tWH tV tXCSH tXCS tDIS 1 Min 5 -26 2 0 2 2 -26 2 Max 2 (+ 25ns1 ) 10 Unit ns ns CLKI cycles ns CLKI cycles CLKI cycles CLKI cycles ns CLKI cycles ns 25ns is when pin loaded with 100pF capacitance. The time is shorter with lower capacitance. Note: As tWL and tWH, as well as tH require at least 2 clock cycles, the maximum speed for the SPI bus that can easily be used is 1/6 of VS1103B's internal clock speed CLKI. Slightly higher speed can be achieved with very careful timing tuning. For details, see Application Notes for VS10XX. Note: Although the timing is derived from the internal clock CLKI, the system always starts up in 1.0x mode, thus CLKI=XTALI. Note: Negative numbers mean that the signal can change in different order from what is shown in the diagram. Version 1.01, 2007-09-03 20 VLSI Solution y VS1103B VS1103B 5. SPI BUSES 5.7 5.7.1 SPI Examples with SM SDINEW and SM SDISHARED set Two SCI Writes SCI Write 1 SCI Write 2 XCS 0 SCK 1 SI 0 0 0 0 0 X 0 0 2 1 0 X 1 2 3 30 31 32 33 61 62 63 DREQ up before finishing next SCI write DREQ Figure 9: Two SCI Operations. Figure 9 shows two consecutive SCI operations. Note that xCS must be raised to inactive state between the writes. Also DREQ must be respected as shown in the figure. 5.7.2 Two SDI Bytes SDI Byte 1 SDI Byte 2 XCS 0 SCK 7 SI 6 5 4 3 1 0 7 6 5 2 1 0 X 1 2 3 6 7 8 9 13 14 15 DREQ Figure 10: Two SDI Bytes. SDI data is synchronized with a raising edge of xCS as shown in Figure 10. However, every byte doesn't need separate synchronization. Version 1.01, 2007-09-03 21 VLSI Solution y VS1103B SCI Operation in Middle of Two SDI Bytes SDI Byte SCI Operation SDI Byte VS1103B 5. SPI BUSES 5.7.3 XCS 0 SCK 1 7 8 9 39 40 41 46 47 7 SI 6 5 1 0 0 0 7 6 5 1 0 X DREQ high before end of next transfer DREQ Figure 11: Two SDI Bytes Separated By an SCI Operation. Figure 11 shows how an SCI operation is embedded in between SDI operations. xCS edges are used to synchronize both SDI and SCI. Remember to respect DREQ as shown in the figure. Version 1.01, 2007-09-03 22 VLSI Solution y VS1103B VS1103B 6. FUNCTIONAL DESCRIPTION 6 6.1 Functional Description Main Features VS1103B is based on a proprietary digital signal processor, VS DSP. It contains all the code and data memory needed for WAV PCM + ADPCM audio decoding, MIDI synthesizer, together with serial interfaces, a multirate stereo audio DAC and analog output amplifiers and filters. Also ADPCM audio encoding is supported using a microphone amplifier and A/D converter. A UART is provided for debugging purposes. 6.2 Supported Audio Codecs 6.2.1 Supported RIFF WAV Formats The most common RIFF WAV subformats are supported. Format 0x01 0x02 0x03 0x06 0x07 0x10 0x11 0x15 0x16 0x30 0x31 0x3b 0x3c 0x40 0x41 0x50 0x55 0x64 0x65 Name PCM ADPCM IEEE FLOAT ALAW MULAW OKI ADPCM IMA ADPCM DIGISTD DIGIFIX DOLBY AC2 GSM610 ROCKWELL ADPCM ROCKWELL DIGITALK G721 ADPCM G728 CELP MPEG MPEGLAYER3 G726 ADPCM G722 ADPCM Supported + + Comments 16 and 8 bits, any sample rate 48kHz Any sample rate 48kHz Version 1.01, 2007-09-03 23 VLSI Solution y VS1103B Supported MIDI Formats VS1103B 6. FUNCTIONAL DESCRIPTION 6.2.2 General MIDI and SP-MIDI format 0 files are played. Format 1 and 2 files must be converted to format 0 by the user. The maximum simultaneous polyphony is 40 (peak polyphony 64). Actual polyphony depends on the internal clock rate (which is user-selectable), the instruments used, and the possible postprocessing effects enabled, such as bass and treble enhancers. The polyphony restriction algorithm makes use of the SP-MIDI MIP table, if present. MIDI implements click-avoiding smooth note removal. When run in Real Time RT-Midi mode without other signal paths, 36.86 MHz (3.0x input clock) achieves 16-26 simultaneous sustained notes. The instantaneous amount of notes can be larger. 36 MHz is a fair compromise between power consumption and quality, but higher clocks can be used to increase polyphony. They are also needed if multiple signal paths are used. Reverb effect can be controlled by the user. In addition to reverb automatic and reverb off modes, 14 different decay times can be selected. These roughly correspond to different room sizes. Also, each midi song decides how much effect each instrument gets. Because the reverb effect uses about 4 MHz of processing power the automatic control enables reverb only when the internal clock is at least 3.0x. When EarSpeaker spatial processing is active, MIDI reverb is not used. VS1103B supports unique instruments in the whole GM1 instrument set and one bank of GM2 percussions. Version 1.01, 2007-09-03 24 VLSI Solution y VS1103B VS1103B 6. FUNCTIONAL DESCRIPTION VS1103B Melodic Intruments (GM1) 1 Acoustic Grand Piano 33 Acoustic Bass 2 Bright Acoustic Piano 34 Electric Bass (finger) 3 Electric Grand Piano 35 Electric Bass (pick) 4 Honky-tonk Piano 36 Fretless Bass 5 Electric Piano 1 37 Slap Bass 1 6 Electric Piano 2 38 Slap Bass 2 7 Harpsichord 39 Synth Bass 1 8 Clavi 40 Synth Bass 2 9 Celesta 41 Violin 10 Glockenspiel 42 Viola 11 Music Box 43 Cello 12 Vibraphone 44 Contrabass 13 Marimba 45 Tremolo Strings 14 Xylophone 46 Pizzicato Strings 15 Tubular Bells 47 Orchestral Harp 16 Dulcimer 48 Timpani 17 Drawbar Organ 49 String Ensembles 1 18 Percussive Organ 50 String Ensembles 2 19 Rock Organ 51 Synth Strings 1 20 Church Organ 52 Synth Strings 2 21 Reed Organ 53 Choir Aahs 22 Accordion 54 Voice Oohs 23 Harmonica 55 Synth Voice 24 Tango Accordion 56 Orchestra Hit 25 Acoustic Guitar (nylon) 57 Trumpet 26 Acoustic Guitar (steel) 58 Trombone 27 Electric Guitar (jazz) 59 Tuba 28 Electric Guitar (clean) 60 Muted Trumpet 29 Electric Guitar (muted) 61 French Horn 30 Overdriven Guitar 62 Brass Section 31 Distortion Guitar 63 Synth Brass 1 32 Guitar Harmonics 64 Synth Brass 2 VS1103B Percussion Intruments (GM1+GM2) 27 High Q 43 High Floor Tom 28 Slap 44 Pedal Hi-hat [EXC 1] 29 Scratch Push [EXC 7] 45 Low Tom 30 Scratch Pull [EXC 7] 46 Open Hi-hat [EXC 1] 31 Sticks 47 Low-Mid Tom 32 Square Click 48 High Mid Tom 33 Metronome Click 49 Crash Cymbal 1 34 Metronome Bell 50 High Tom 35 Acoustic Bass Drum 51 Ride Cymbal 1 36 Bass Drum 1 52 Chinese Cymbal 37 Side Stick 53 Ride Bell 38 Acoustic Snare 54 Tambourine 39 Hand Clap 55 Splash Cymbal 40 Electric Snare 56 Cowbell 41 Low Floor Tom 57 Crash Cymbal 2 42 Closed Hi-hat [EXC 1] 58 Vibra-slap 65 Soprano Sax 66 Alto Sax 67 Tenor Sax 68 Baritone Sax 69 Oboe 70 English Horn 71 Bassoon 72 Clarinet 73 Piccolo 74 Flute 75 Recorder 76 Pan Flute 77 Blown Bottle 78 Shakuhachi 79 Whistle 80 Ocarina 81 Square Lead (Lead 1) 82 Saw Lead (Lead) 83 Calliope Lead (Lead 3) 84 Chiff Lead (Lead 4) 85 Charang Lead (Lead 5) 86 Voice Lead (Lead 6) 87 Fifths Lead (Lead 7) 88 Bass + Lead (Lead 8) 89 New Age (Pad 1) 90 Warm Pad (Pad 2) 91 Polysynth (Pad 3) 92 Choir (Pad 4) 93 Bowed (Pad 5) 94 Metallic (Pad 6) 95 Halo (Pad 7) 96 Sweep (Pad 8) 97 Rain (FX 1) 98 Sound Track (FX 2) 99 Crystal (FX 3) 100 Atmosphere (FX 4) 101 Brightness (FX 5) 102 Goblins (FX 6) 103 Echoes (FX 7) 104 Sci-fi (FX 8) 105 Sitar 106 Banjo 107 Shamisen 108 Koto 109 Kalimba 110 Bag Pipe 111 Fiddle 112 Shanai 113 Tinkle Bell 114 Agogo 115 Pitched Percussion 116 Woodblock 117 Taiko Drum 118 Melodic Tom 119 Synth Drum 120 Reverse Cymbal 121 Guitar Fret Noise 122 Breath Noise 123 Seashore 124 Bird Tweet 125 Telephone Ring 126 Helicopter 127 Applause 128 Gunshot 59 Ride Cymbal 2 60 High Bongo 61 Low Bongo 62 Mute Hi Conga 63 Open Hi Conga 64 Low Conga 65 High Timbale 66 Low Timbale 67 High Agogo 68 Low Agogo 69 Cabasa 70 Maracas 71 Short Whistle [EXC 2] 72 Long Whistle [EXC 2] 73 Short Guiro [EXC 3] 74 Long Guiro [EXC 3] 75 Claves 76 Hi Wood Block 77 Low Wood Block 78 Mute Cuica [EXC 4] 79 Open Cuica [EXC 4] 80 Mute Triangle [EXC 5] 81 Open Triangle [EXC 5] 82 Shaker 83 Jingle bell 84 Bell tree 85 Castanets 86 Mute Surdo [EXC 6] 87 Open Surdo [EXC 6] Version 1.01, 2007-09-03 25 VLSI Solution y VS1103B VS1103B 6. FUNCTIONAL DESCRIPTION 6.3 6.3.1 Data Flow of VS1103B Normal Data Flow Gain 1 UART SCI MIDI stream Buffer 1 Gain 2 SDI SM_ICONF AGC/Gain 4 A/D stream A/D GAIN3 != 0 ADPCM stream Buffer 2 Mixer Audio stream Gain 3 44.1 kHz SM_RECORD_PATH=1 8 kHz SM_RECORD_PATH=0 ADPCM encode SM_ADPCM=1 Buffer 3 Stream 4 SCI * Only one MIDI and one ADPCM stream may be active at the time **UART can only be used for real-time MIDI Figure 12: Normal Data Flow of VS1103B, Part 1. Generation of the Audio stream and recording A/D stream is presented in Figure 12. Stream 1, which is the MIDI stream, may be fed either through SDI, SCI or UART. If it is fed through UART, real-time MIDI, or RT-MIDI is assumed. The buffer size is 1024 bytes. Stream 2, which is the ADPCM stream, may be fed either through SDI or SCI. The buffer size is 1024 bytes. Stream 3, which is the A/D stream, running always at 8 kHz, is active if register SM ADPCM is set. The outputs of the three streams are forwarded to the Mixer, which resamples all data to 44.1 kHz, and forwards the data. Either one of the A/D stream and the output of the Mixer can be fed to ADPCM encoding. If the data is read from the A/D stream, it will be encoded as 8 kHz mono and if it is read from the Mixer, it will encode as 44.1 kHz mono. The ADPCM compressed data may be read from SCI registers SCI IN0 and SCI IN1. The buffer size is 1024 bytes. Version 1.01, 2007-09-03 26 VLSI Solution y VS1103B VS1103B 6. FUNCTIONAL DESCRIPTION AIADDR=0 Audio stream SB_AMPLITUE=0 ST_AMPLITUDE=0 ST_EARSPEAKER=0 User application AIADDR!=0 Bass enhancer SB_AMPLITUDE!=0 Treble enhancer ST_AMPLITUDE!=0 Earspeaker ST_EARSPEAKER!=0 Volume control SCI_VOL Audio FIFO 512 stereo samples L S.rate.conv R and DAC Figure 13: Normal Data Flow of VS1103B, Part 2. Figure 13 presents the data flow of the Audio stream generated in Figure 12. If SCI AIADDR is non-zero, application code is executed from the address pointed to by that register. For more details, see Application Notes for VS10XX. Then data may be sent to the Bass and Treble Enhancer depending on the SCI BASS register, followed by Earspeaker Spatial Processing, depending on ST EARSPEAKER. After that the signal is fed to the volume control unit, which also copies the data to the Audio FIFO. The Audio FIFO holds the data, which is read by the Audio interrupt (Chapter 8.13.1) and fed to the sample rate converter and DACs. The size of the audio FIFO is 1024 stereo (2x16-bit) samples, or 4 KiB. The sample rate converter converts all different sample rates to XTALI/2, or 128 times the highest usable sample rate. This removes the need for complex PLL-based clocking schemes and allows almost unlimited sample rate accuracy with one fixed input clock frequency. With a 12.288 MHz clock, the DA converter operates at 128 x 48 kHz, i.e. 6.144 MHz, and creates a stereo in-phase analog signal. The oversampled output is low-pass filtered by an on-chip analog filter. This signal is then forwarded to the earphone amplifier. 6.3.2 Real-Time RT-Midi Mode If GPIO1 is 1 and GPIO0 is 0 at startup, RT-Midi Mode is activated. In this mode RT-Midi data is read through the UART at the default MIDI speed 31250 bit/s. The generated audio is sent to the audio path as shown in Figure 13. When RT-MIDI mode is activated, GPIO2 and GPIO3 are read and their contents are copied to register bits SCIMB EARSPEAKER0 and SCIMB EARSPEAKER1, respectively. This way it is possible to activate EarSpeaker in this mode without writing to any SCI registers. Also, if SCI CLOCKF has not been set to a non-zero value, the clock multiplier is automatically set to 3.5X. This mode is intended for connecting a MIDI keyboard or sequencer to VS1103B. Version 1.01, 2007-09-03 27 VLSI Solution y VS1103B VS1103B 6. FUNCTIONAL DESCRIPTION 6.4 Serial Data Interface (SDI) The serial data interface is meant for transferring ADPCM or MIDI data. If the input of the decoder is invalid or it is not received fast enough, analog outputs are automatically muted. Also several different tests may be activated through SDI as described in Chapter 7. 6.5 Serial Control Interface (SCI) The serial control interface is compatible with the SPI bus specification. Data transfers are always 16 bits. VS1103B is controlled by writing and reading the registers of the interface. The main controls of the control interface are: * * * * control of the operation mode, clock, and builtin effects access to status information and header data access to encoded digital data uploading user programs 6.6 SCI Registers SCI registers, prefix SCI Time1 Abbrev[bits] 200 CLKI4 MODE 40 CLKI STATUS 2100 CLKI BASS 11000 XTALI5 CLOCKF 40 CLKI DECODE TIME 3200 CLKI AUDATA 80 CLKI WRAM 80 CLKI WRAMADDR 90 CLKI IN0 90 CLKI IN1 3200 CLKI2 AIADDR 2100 CLKI VOL 70 CLKI2 MIXERVOL 50 CLKI2 ADPCMRECCTL 50 CLKI2 AICTRL2 50 CLKI2 AICTRL3 Reg 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF 1 Type rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Reset 0x800 0x3C3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Description Mode control Status of VS1103B Built-in bass/treble enhancer Clock freq + multiplier Stream 0 decode time Misc. audio data RAM write/read Base address for RAM write/read Input 0 Input 1 Start address of application Volume control Mixer volume IMA ADPCM record control Application control register 2 Application control register 3 This is the worst-case time that DREQ stays low after writing to / reading from this register. The user may choose to skip the DREQ check for those register writes that take less than 100 clock cycles to execute. Version 1.01, 2007-09-03 28 VLSI Solution y 2 3 VS1103B VS1103B 6. FUNCTIONAL DESCRIPTION In addition, the cycles spent in the user application routine must be counted. Firmware changes the value of this register immediately after reset to 0x38, and in less than 100 ms to 0x30. 4 5 When mode register write specifies a software reset the worst-case time is 16600 XTALI cycles. Writing to this register may force internal clock to run at 1.0 x XTALI for a while. Thus it is not a good idea to send SCI or SDI bits while this register update is in progress. Note: it is not allowed to do an SCI operation while DREQ is low. If this is done, however, DREQ stays low even after the SCI operation has been processed. 6.6.1 SCI MODE (RW) SCI MODE is used to control the operation of VS1103B and defaults to 0x0800 (SM SDINEW set). SCI MODE bits Function Differential Choose ADPCM recording path Soft reset Cancel MIDI decoding Powerdown Allow SDI tests Input configuration Name SM DIFF SM RECORD PATH SM RESET SM OUTOFMIDI SM PDOWN SM TESTS SM ICONF Bit 0 1 2 3 4 5 7:6 SM DACT SM SDIORD SM SDISHARE SM SDINEW SM EARSPEAKER 8 9 10 11 13:12 DCLK active edge SDI bit order Share SPI chip select VS1002 native SPI modes Earspeaker setting SM LINE IN SM ADPCM 14 15 A/D stream input selector ADPCM recording active Value 0 1 0 1 0 1 0 1 0 1 0 1 0 1 2 3 0 1 0 1 0 1 0 1 0 1 2 3 0 1 0 1 Description normal in-phase audio left channel inverted A/D stream Mixer output no reset reset no yes power on powerdown not allowed allowed SDI MIDI, SCI ADPCM SCI MIDI, SDI ADPCM UART RT-MIDI, SCI ADPCM UART RT-MIDI, SDI ADPCM rising falling MSb first MSb last no yes no yes off low mid high microphone line in no yes Version 1.01, 2007-09-03 29 VLSI Solution y VS1103B VS1103B 6. FUNCTIONAL DESCRIPTION When SM DIFF is set, the player inverts the left channel output. For a stereo input this creates virtual surround, and for a mono input this creates a differential left/right signal. If SM RECORD PATH is set, ADPCM recording is performed from the A/D stream at 8 kHz, otherwise the Mixer output is recorded at 44.1 kHz. This bit is only valid if SM ADPCM is set. Software reset is initiated by setting SM RESET to 1. This bit is cleared automatically. To stop decoding a MIDI file set SM OUTOFMIDI, and send data until SM OUTOFMIDI has cleared. If SM OUTOFMIDI is set while MIDI decoding has not been going on, the register bit will not be cleared before the few first words of the next MIDI file (or zeros) have been sent to the decoder. Bit SM PDOWN sets VS1103B into software powerdown mode where the only operational software part is the control bus handler. Note: software powerdown is not nearly as power efficient as hardware powerdown activated with the XRESET pin. If SM TESTS is set, SDI tests are allowed. For more details on SDI tests, look at Chapter 7.8. SM ICONF specifies the configuration of the data input streams. The following table shows its bits. SM ICONF S1 Port Stream1 S2 Port Stream2 0 SDI MIDI SCI ADPCM 1 SCI MIDI SDI ADPCM 2 UART/SDI RT-MIDI/RT-SDI SCI ADPCM 3 UART RT-MIDI SDI ADPCM When SM ICONF is set to 2, Real Time MIDI messages can be sent either through the UART or SDI. If sent through UART, the standard MIDI protocol and date speed (31250 bit/s) is used. If send through SDI, the protocol is otherwise the same, but every byte must either be preceded or followed by a zero byte (but only one of these two alternative zero byte orders may be used at a time). So, a message that would be sent as 0x92 0x37 0x73 through normal MIDI, would become 0x92 0x00 0x37 0x00 0x73 0x00 if sent through SDI. NOTE! If you change SM ICONF, a software reset is performed as if you had also set SM RESET! SM DACT defines the active edge of data clock for SDI. When '0', data is read at the rising edge, when '1', data is read at the falling edge. When SM SDIORD is clear, bytes on SDI are sent as a default MSb first. By setting SM SDIORD, the user may reverse the bit order for SDI, i.e. bit 0 is received first and bit 7 last. Bytes are, however, still sent in the default order. This register bit has no effect on the SCI bus. Setting SM SDISHARE makes SCI and SDI share the same chip select, as explained in Chapter 5.2, if also SM SDINEW is set. Setting SM SDINEW will activate VS1002 native serial modes as described in Chapters 5.2.1 and 5.4.2. Note, that this bit is set as a default when VS1103B is started up. Version 1.01, 2007-09-03 30 VLSI Solution y VS1103B VS1103B 6. FUNCTIONAL DESCRIPTION Bits in SM EARSPEAKER control EarSpeaker spatial processing. They are used as follows: SM EARSPEAKER Setting 0 Off 1 Minimal 2 Normal 3 Extreme EarSpeaker uses approximately 6 MIPS at 44.1 kHz sample rate. SM LINE IN is used to select the input for ADPCM recording. If '0', microphone input pins MICP and MICN are used; if '1', LINEIN is used. When SM ADPCM is turned on, ADPCM encoding is activated (see Image 12 at Page 26). 6.6.2 SCI STATUS (RW) SCI STATUS contains information on the current status of VS1103B and lets the user shutdown the chip without audio glitches. Name SS VER SS APDOWN2 SS APDOWN1 SS AVOL Bits 7:4 3 2 1:0 Description Version Analog driver powerdown Analog internal powerdown Analog volume control SS VER is 0 for VS1001, 1 for VS1011, 2 for VS1002, 3 for VS1003, 4 for VS1053, 5 for VS1033, and 7 for VS1103. SS APDOWN2 controls analog driver powerdown. Normally this bit is controlled by the system firmware. However, if the user wants to powerdown VS1103B with a minimum power-off transient, turn this bit to 1, then wait for at least a few milliseconds before activating reset. SS APDOWN1 controls internal analog powerdown. This bit is meant to be used by the system firmware only. SS AVOL is the analog volume control: 0 = -0 dB, 1 = -6 dB, 3 = -12 dB. This register is meant to be used automatically by the system firmware only. 6.6.3 SCI BASS (RW) Bits 15:12 11:8 7:4 3:0 Description Treble Control in 1.5 dB steps (-8..7, 0 = off) Lower limit frequency in 1000 Hz steps (0..15) Bass Enhancement in 1 dB steps (0..15, 0 = off) Lower limit frequency in 10 Hz steps (2..15) Name ST AMPLITUDE ST FREQLIMIT SB AMPLITUDE SB FREQLIMIT The Bass Enhancer VSBE is a powerful bass boosting DSP algorithm, which tries to take the most out Version 1.01, 2007-09-03 31 VLSI Solution y VS1103B VS1103B 6. FUNCTIONAL DESCRIPTION of the users earphones without causing clipping. VSBE is activated when SB AMPLITUDE is non-zero. SB AMPLITUDE should be set to the user's preferences, and SB FREQLIMIT to roughly 1.5 times the lowest frequency the user's audio system can reproduce. For example setting SCI BASS to 0x00a6 will give 15 dB enhancement below 60 Hz. Note: Because VSBE tries to avoid clipping, it gives the best bass boost with dynamical music material, or when the playback volume is not set to maximum. It also does not create bass from nothing: the source material must have some bass to begin with. Treble Control VSTC is activated when ST AMPLITUDE is non-zero. For example setting SCI BASS to 0x7a00 will give 10.5 dB treble enhancement above 10 kHz. Bass Enhancer uses about 3.0 MIPS and Treble Control 1.2 MIPS at 44100 Hz sample rate. Both can be on simultaneously. 6.6.4 SCI CLOCKF (RW) SCI CLOCKF is used to control the internal clock of VS1103B. SCI CLOCKF bits Name Bits Description SC MULT 15:13 Clock multiplier SC ZERO 12:11 Set to zero SC FREQ 10: 0 Clock frequency SC MULT activates the built-in clock multiplier. This will multiply XTALI to create a higher CLKI. The values are as follows: SC MULT 0 1 2 3 4 5 6 7 MASK 0x0000 0x2000 0x4000 0x6000 0x8000 0xa000 0xc000 0xe000 CLKI XTALI XTALIx1.5 XTALIx2.0 XTALIx2.5 XTALIx3.0 XTALIx3.5 XTALIx4.0 XTALIx4.5 SC FREQ is used to tell if the input clock XTALI is running at something else than 12.288 MHz. XTALI is set in 4 kHz steps. The formula for calculating the correct value for this register is XT ALI-8000000 4000 (XTALI is in Hz). Note: As opposed to some other VS10XX chips, a software reset must be performed after SCI CLOCKF has been set. It is recommended that SCI CLOCKF is set only after each hardware reset / startup. Note: The default value 0 is assumed to mean XTALI=12.288 MHz. Version 1.01, 2007-09-03 32 VLSI Solution y VS1103B XT ALI 256 , VS1103B 6. FUNCTIONAL DESCRIPTION Note: Because maximum sample rate is MHz. all sample rates are not available if XTALI < 12.288 Example: If SCI CLOCKF is 0xC3E8, SC MULT = 6 and SC FREQ = 0x3E8 = 1000. This means that XTALI = 1000 x 4000 + 8000000 = 12 MHz. The clock multiplier is set to 4.0xXTALI = 48 MHz. 6.6.5 SCI DECODE TIME (RW) When decoding correct MIDI data, current decoded time is shown in this register in full seconds. The user may change the value of this register. In that case the new value should be written twice. SCI DECODE TIME is reset at every software reset and also when MIDI decoding starts or ends. 6.6.6 SCI AUDATA (RW) The current sample rate and number of channels can be found in bits 15:1 and 0 of SCI AUDATA, respectively. Bits 15:1 contain the sample rate divided by two, and bit 0 is 0 for mono data and 1 for stereo. Writing to SCI AUDATA will change the sample rate directly (not recommended for VS1103B!). As VS1103B always runs in stereo mode at 44100 Hz, contents of this register is always 0xAC45 (44101). 6.6.7 SCI WRAM (RW) SCI WRAM is used to upload application programs and data to instruction and data RAMs. The start address must be initialized by writing to SCI WRAMADDR prior to the first write/read of SCI WRAM. As 16 bits of data can be transferred with one SCI WRAM write/read, and the instruction word is 32 bits long, two consecutive writes/reads are needed for each instruction word. The byte order is big-endian (i.e. most significant byte first). After each full-word write/read, the internal pointer is autoincremented. 6.6.8 SCI WRAMADDR (W) SCI WRAMADDR is used to set the program address for following SCI WRAM writes/reads. Address offset of 0 is used for X, 0x4000 for Y, and 0x8000 for instruction memory. Peripheral registers can also be accessed. SM WRAMADDR Start. . . End 0x1800. . . 0x187F 0x5800. . . 0x587F 0x8030. . . 0x84FF 0xC000. . . 0xFFFF Dest. addr. Start. . . End 0x1800. . . 0x187F 0x1800. . . 0x187F 0x0030. . . 0x04FF 0xC000. . . 0xFFFF Bits/ Word 16 16 32 16 Description X data RAM Y data RAM Instruction RAM I/O Version 1.01, 2007-09-03 33 VLSI Solution y VS1103B VS1103B 6. FUNCTIONAL DESCRIPTION Only user areas in X, Y, and instruction memory are listed above. Other areas can be accessed, but should not be written to unless otherwise specified. 6.6.9 SCI IN0 and SCI IN1 (R) SCI IN0 and SCI IN1 are used for offering SCI stream data and for reading encoded ADPCM Stream 4 data. The bits in the registers are as follows: Register SCI IN0 SCI IN0 SCI IN1 SCI IN1 R/W Read Write Read Read Bits/ 15:0 15:0 15:8 7:0 Description Read one word from Stream 4 Write one word to SCI sourced stream Number of words x8 that can be read from SCI IN0 (Stream 4) Number of words x8 that can be written to SCI IN0 (SCI sourced stream) Note: Data word length is 16 bits. Example: If reading SCI IN1 returns 0x0312, then 0x03x8 words = 24 words = 48 bytes can be read from SCI IN0 and 0x12x8 words = 144 words = 288 bytes can be written to SCI IN0. 6.6.10 SCI AIADDR (RW) SCI AIADDR indicates the start address of the application code written earlier with SCI WRAMADDR and SCI WRAM registers. If no application code is used, this register should not be initialized, or it should be initialized to zero. For more details, see Application Notes for VS10XX. 6.6.11 SCI VOL (RW) SCI VOL is a volume control for the player hardware. For each channel, a value in the range of 0..254 may be defined to set its attenuation from the maximum volume level (in 0.5 dB steps). The left channel value is then multiplied by 256 and the values are added. Thus, maximum volume is 0 and total silence is 0xFEFE. Example: for a volume of -2.0 dB for the left channel and -3.5 dB for the right channel: (4*256) + 7 = 0x407. Note, that at startup volume is set to full volume. Resetting the software does not reset the volume setting. Note: Setting SCI VOL to 0xFFFF will activate analog powerdown mode. Version 1.01, 2007-09-03 34 VLSI Solution y VS1103B SCI MIXERVOL (RW) VS1103B 6. FUNCTIONAL DESCRIPTION 6.6.12 Control mixer volume. The contents of this register is as follows: SCI MIXERVOL bits Name Bits Description SMV ACTIVE 15 Control active SMV GAIN3 14:10 Gain 3 SMV GAIN2 9:5 Gain 2 SMV GAIN1 4:0 Gain 1 Gain values are defined in 1 dB steps so that 25 corresponds to 0 dB (signal is passed on as is) and 31 is +6 dB (signal is doubled). 0 means the channel is disabled. If SMV ACTIVE is 0, then Gain 1 is set to 25 (0 dB), and both Gain 2 and Gain 3 are set to 0 (mute). See Figure 12 on page 26 for more details on where gains are applied. Note: The polarity of the gains are opposite to registr SCI VOL: higher means a higher gain, not higher attenuation. 6.6.13 SCI ADPCMRECCTL (RW) SCI Bits 8 7 6 5:0 ADPCMRECCTL bits Description If set, DREQ needs 512 byte space to turn on. If set, current ADPCM playback is canceled. If set, automatic gain control (AGC) is not in used. If SARC MANUALGAIN is 1, this is Gain 4; otherwise it is maximum gain of AGC Name SARC SARC SARC SARC DREQ512 OUTOFADPCM MANUALGAIN GAIN4 SARC DREQ512 affects how the DREQ pin works. If not set, when DREQ is active there is at least 32 bytes space to write to. If set, DREQ is set only when there is at least 512 bytes of free space in the SDI input buffer. SARC OUTOFADPCM does same to ADPCM playback as SCI MODE register bit SM OUTOFMIDI does to MIDI playback. Thus, if you want to stop decoding an ADPCM file, set SARC OUTOFADPCM, and send data until SARC OUTOFADPCM is cleared. SARC MANUALGAIN controls whether Gain 4 is manual or automatic. If SARC MANUALGAIN is set to 1, SARC GAIN4 sets Gain 4. Otherwise SARC GAIN4 sets the maximum gain allowed for the automatic gain control. The value is set at 1 dB steps and value 25 means 0 dB gain (signal is passed on without change). 31 is equal to to +6 dB gain, etc. 0 disables the signal path completely. Version 1.01, 2007-09-03 35 VLSI Solution y VS1103B SCI AICTRL[x] (RW) VS1103B 6. FUNCTIONAL DESCRIPTION 6.6.14 SCI AICTRL[x] registers ( x=[0 .. 3] ) can be used to access the user's application program. Note: VS1103B reservs AICTRL0 as SCI MIXERVOL and AICTRL1 as SCI ADPCMRECCTL. They can, however, also be used for user applications if the applications don't conflict with the originally intended register contents. Version 1.01, 2007-09-03 36 VLSI Solution y VS1103B VS1103B 7. OPERATION 7 7.1 Operation Clocking VS1103B operates on a single, nominally 12.288 MHz fundamental frequency master clock. This clock can be generated by external circuitry (connected to pin XTALI) or by the internal clock crystal interface (pins XTALI and XTALO). 7.2 Hardware Reset When the XRESET -signal is driven low, VS1103B is reset and all the control registers and internal states are set to the initial values. XRESET-signal is asynchronous to any external clock. The reset mode doubles as a full-powerdown mode, where both digital and analog parts of VS1103B are in minimum power consumption stage, and where clocks are stopped. Also XTALO is grounded. After a hardware reset (or at power-up) DREQ will stay down for at least 16600 clock cycles, which means an approximate 1.35 ms delay if VS1103B is run at 12.288 MHz. After this the user should set SCI CLOCKF, perform a software reset, and then set other basic software registers as e.g. SCI MODE, SCI BASS, and SCI VOL before starting decoding. See section 6.6 for details. The internal clock can be multiplied with a PLL. Supported multipliers through the SCI CLOCKF register are 1.0 x . . . 4.5x the input clock. Reset value for Internal Clock Multiplier is 1.0x. If typical values are wanted, the Internal Clock Multiplier needs to be set to 4.0x after reset. Wait until DREQ rises, then write a proper value to SCI CLOCKF, followed by a software reset. See section 6.6.4 for details. After XRESET is released, a software reset operation is also performed. 7.3 Software Reset In some cases the decoder software has to be reset. This is done by activating bit 2 in SCI MODE register (Chapter 6.6.1). Then wait for at least 2 s, then look at DREQ. DREQ will stay down for at least 16600 clock cycles, which means an approximate 1.35 ms delay if VS1103B is run at 12.288 MHz. After DREQ is up, you may continue playback as usual. If GPIO0 is set to 1, Spi Boot is performed (Chapter 7.5). If GPIO0 is set to 0 and GPIO1 to 1, RT-MIDI Mode is activated (Chapter 6.3.2). As opposed to some earlier VS10XX products, VS1103B has been designed so that using software resets during normal operation shouldn't be necessary. Version 1.01, 2007-09-03 37 VLSI Solution y VS1103B VS1103B 7. OPERATION 7.4 ADPCM Recording This chapter explains how to create RIFF/WAV file with IMA ADPCM format. This is a widely supported ADPCM format and many PC audio playback programs can play it. IMA ADPCM recording gives roughly a compression ratio of 4:1 compared to linear, 16-bit audio. This makes it possible to record approx. 8 kHz audio at approx. 32.44 kbit/s or 44.1 kHz audio at 178.85 kbit/s. 7.4.1 Activating ADPCM Recording IMA ADPCM recording mode is activated by setting bit SM ADPCM in SCI MODE. Before activating ADPCM recording, user must see to it that SCI ADPCMRECCTL has been properly set. 7.4.2 Reading IMA ADPCM Data After IMA ADPCM recording has been activated, results can be read through registers SCI IN0 and SCI IN1. The IMA ADPCM sample buffer size is 512 16-bit words, or 1 KiB. If the data is not read fast enough, the buffer overflows and returns to empty state. Each IMA ADPCM block consists of 128 words, i.e. 256 bytes (or 505 mono audio samples). If you wish to interrupt reading data and possibly continue later, please stop at a 128-word boundary. This way whole blocks are skipped and the encoded stream stays valid. Note: if SCI IN1[15:8] 60 (i.e. there are more than 60 x 8 = 480 words waiting), wait for the buffer to overflow and clear before reading samples to avoid buffer aliasing. Version 1.01, 2007-09-03 38 VLSI Solution y VS1103B Adding a RIFF Header VS1103B 7. OPERATION 7.4.3 To make your IMA ADPCM file a RIFF / WAV file, you have to add a header before the actual data. Note that 2- and 4-byte values are little-endian (lowest byte first) in this format: File Offset 0 4 8 12 16 20 22 24 28 32 34 36 38 40 44 48 52 56 60 316 Field Name ChunkID ChunkSize Format SubChunk1ID SubChunk1Size AudioFormat NumOfChannels SampleRate ByteRate BlockAlign BitsPerSample ByteExtraData ExtraData SubChunk2ID SubChunk2Size NumOfSamples SubChunk3ID SubChunk3Size Block1 ... Size 4 4 4 4 4 2 2 4 4 2 2 2 2 4 4 4 4 4 256 Bytes "RIFF" F0 F1 F2 F3 "WAVE" "fmt " 0x14 0x0 0x0 0x0 0x11 0x0 0x1 0x0 R0 R1 R2 R3 B0 B1 B2 B3 0x0 0x1 0x4 0x0 0x2 0x0 0xf9 0x1 "fact" 0x4 0x0 0x0 0x0 S0 S1 S2 S3 "data" D0 D1 D2 D3 Description File size - 8 20 0x11 for IMA ADPCM Mono sound 0x1f40 for 8 kHz 0xfd7 for 8 kHz 0x100 4-bit ADPCM 2 Samples per block (505) 4 Data size (File Size-60) First ADPCM block More ADPCM data blocks If we have n audio blocks, the values in the table are as follows: F = n x 256 + 52 R = Fs (see Chapter 7.4.1 to see how to calculate Fs ) x256 B = Fs505 S = n x 505. D = n x 256 If you know beforehand how much you are going to record, you may fill in the complete header before any actual data. However, if you don't know how much you are going to record, you have to fill in the header size datas F , S and D after finishing recording. The 128 words (256 bytes) of an ADPCM block are read from SCI IN0 and written into file as follows. The high 8 bits of SCI IN0 should be written as the first byte to a file, then the low 8 bits. Note that this is contrary to the default operation of some 16-bit microcontrollers, and you may have to take extra care to do this right. A way to see if you have written the file in the right way is to check bytes 2 and 3 (the first byte counts as byte 0) of each 256-byte block. Byte 2 should always be less than 90, and byte 3 should always be zero. Version 1.01, 2007-09-03 39 VLSI Solution y VS1103B Playing ADPCM Data VS1103B 7. OPERATION 7.4.4 In order to play back your IMA ADPCM recordings, you have to have a file with a header as described in Chapter 7.4.3. If this is the case, all you need to do is to provide the ADPCM file to VS1103 as an ADPCM stream. 7.4.5 Sample Rate Considerations VS10xx chips that support IMA ADPCM playback are capable of playing back ADPCM files with any sample rate. However, some other programs may expect IMA ADPCM files to have some exact sample rates, like 8000 or 11025 Hz. Also, some programs or systems do not support sample rates below 8000 Hz. If SM RECORD PATH is set, recording is performed from the mixer output at exactly 44.1 kHz from XT ALI the mixer output. If SM RECORD PATH is not set, recording is performed at 8kHz x 12.288M Hz from the microphone or line input. From the formula it can be seen that the nominal 8 kHz sample rate can only be obtained if XTALI = 12.288 MHz. Example: If you have a 12 MHz clock, you will get a sample rate of 7812.5 Hz, which should be recorded to the file. 7.4.6 Example Code The following code initializes IMA ADPCM encoding on VS1103 and shows how to read the data. const unsigned char 0x52, 0x49, 0x46, 0x57, 0x41, 0x56, 0x14, 0x00, 0x00, 0x40, 0x1f, 0x00, 0x00, 0x01, 0x04, 0x66, 0x61, 0x63, 0x5c, 0x1f, 0x00, 0xe8, 0x0f, 0x00, }; header[] = { 0x46, 0x1c, 0x10, 0x45, 0x66, 0x6d, 0x00, 0x11, 0x00, 0x00, 0x75, 0x12, 0x00, 0x02, 0x00, 0x74, 0x04, 0x00, 0x00, 0x64, 0x61, 0x00 0x00, 0x74, 0x01, 0x00, 0xf9, 0x00, 0x74, 0x00, 0x20, /*|RIFF....WAVEfmt |*/ 0x00, 0x00, /*|........@......|*/ 0x01, 0x00, /*|.......fact....|*/ 0x61, unsigned char db[512]; /* data buffer for saving to disk */ Version 1.01, 2007-09-03 40 VLSI Solution y VS1103B VS1103B 7. OPERATION void RecordAdpcm1103(void) { /* VS1003b/VS1023 */ u_int16 w = 0, idx = 0, n = 0; s_int32 adpcmBlocks = -1; ... /* Check and locate free space on disk */ 4.0x 12.288MHz */ Wait for DREQ to go up again */ Normal SW reset + other bits */ Wait for DREQ to go up again */ Recording monitor volume */ Bass/treble disabled */ (23<<10) | (23<<5) | (23)); /* Auto gain to max +20 dB */ Line in, SDI MIDI, SCI ADPCM, 8 kHz */ WriteMp3SpiReg(SCI_CLOCKF, 0xC3E8); /* WaitForDreq(); /* WriteMp3SpiReg(SCI_MODE, 0x0804); /* WaitForDreq(); /* WriteMp3SpiReg(SCI_VOL, 0x1414); /* WriteMp3SpiReg(SCI_BASS, 0); /* WriteMp3SpiReg(SCI_MIXERVOL, 0x8000U | WriteMp3SpiReg(SCI_ADPCMRECCTL,25+20); WriteMp3SpiReg(SCI_MODE, 0x08c8); /* for (idx=0; idx < sizeof(header); idx++) /* Save header first */ db[idx] = header[idx]; db[24] = sampleRate; /* Set sample rate */ db[25] = samplRate>>8; /* Synchronize */ do { n = 8 * ((ReadMp3SpiReg(SCI_IN1) >> 8) & 0xFF); Yield(1); /* Give control to other processes for 1 ms */ } while (n >= 480); /* whole buffer size = 512 words */ /* Record loop */ while (recording_on) { while (idx < 512) { do { n = 8 * ((ReadMp3SpiReg(SCI_IN1) >> 8) & 0xFF); Yield(1); /* Give control to other processes for 1 ms */ } while (n < 16); /* Only load data if >= 16 words available */ while (n--) { w = ReadMp3SpiReg(SCI_IN0); db[idx++] = w>>8; db[idx++] = w&0xFF; } } idx = 0; write_block(datasector++, db); /* Write one disk block */ adpcmBlocks+=2; /* Disk block contains 2 adpcm blocks */ } if (adpcmBlocks >= 0) { /* The previous algorithm will always write an unfinished ADPCM block. It doesn't matter as we consistently only tell of the data until the last completely written block. */ dataSizeD = adpcmBlocks*256; chunkSizeF = dataSizeD+52: numOfSamplesS = adpcmBlocks*505; ... /* Fix WAV header information */ } } Version 1.01, 2007-09-03 41 VLSI Solution y VS1103B VS1103B 7. OPERATION 7.5 SPI Boot If GPIO0 is set with a pull-up resistor to 1 at boot time, VS1103B tries to boot from external SPI memory. SPI boot redefines the following pins: Normal Mode GPIO0 GPIO1 DREQ GPIO2 SPI Boot Mode xCS CLK MOSI MISO The memory has to be an SPI Bus Serial EEPROM with 16-bit addresses (i.e. at least 1 KiB). The serial speed used by VS1103B is 245 kHz with the nominal 12.288 MHz clock. The first three bytes in the memory have to be 0x50, 0x26, 0x48. The exact record format is explained in the Application Notes for VS10XX. 7.6 Play/Decode This is the normal operation mode of VS1103B. MIDI and ADPCM are decoded, mixed and converted to analog domain by the internal DAC. When there is no input for decoding, VS1103B goes into idle mode (lower power consumption than during decoding) and actively monitors the serial data input for valid data. All different formats can be played back-to-back without software resets in-between. Send at least 4 zeros after each stream. 7.7 Feeding PCM data VS1103B can be used as a PCM decoder by sending to it a WAV file header. If the length sent in the WAV file is 0xFFFFFFFF, VS1103B will stay in PCM mode for a long time (or until SARC OUTOFADPCM has been set). 8-bit linear and 16-bit linear audio is supported in mono or stereo. 7.8 SDI Tests There are several test modes in VS1103B, which allow the user to perform memory tests, SCI bus tests, and several different sine wave tests. All tests are started in a similar way: VS1103B is hardware reset, SM TESTS is set, and then a test command is sent to the SDI bus. Each test is started by sending a 4-byte special command sequence, followed by 4 zeros. The sequences are described below. Version 1.01, 2007-09-03 42 VLSI Solution y VS1103B Sine Test VS1103B 7. OPERATION 7.8.1 Sine test is initialized with the 8-byte sequence 0x53 0xEF 0x6E n 0 0 0 0, where n defines the sine test to use. n is defined as follows: n bits Description Sample rate index Sine skip speed Fs 44100 Hz 48000 Hz 32000 Hz 22050 Hz 24000 Hz 16000 Hz 11025 Hz 12000 Hz S 128 . Name F s Idx S Bits 7:5 4:0 F s Idx 0 1 2 3 4 5 6 7 The frequency of the sine to be output can now be calculated from F = F s x Example: Sine test is activated with value 126, which is 0b01111110. Breaking n to its components, F s Idx = 0b011 = 3 and thus F s = 22050Hz. S = 0b11110 = 30, and thus the final sine frequency 30 F = 22050Hz x 128 5168Hz. To exit the sine test, send the sequence 0x45 0x78 0x69 0x74 0 0 0 0. Note: Sine test signals go through the digital volume control, so it is possible to test channels separately. 7.8.2 Pin Test Pin test is activated with the 8-byte sequence 0x50 0xED 0x6E 0x54 0 0 0 0. This test is meant for chip production testing only. Version 1.01, 2007-09-03 43 VLSI Solution y VS1103B Memory Test VS1103B 7. OPERATION 7.8.3 Memory test mode is initialized with the 8-byte sequence 0x4D 0xEA 0x6D 0x54 0 0 0 0. After this sequence, wait for 500000 clock cycles. The result can be read from the SCI register SCI IN0, and 'one' bits are interpreted as follows: Bit(s) 15 14:7 6 5 4 3 2 1 0 Mask 0x8000 0x0040 0x0020 0x0010 0x0008 0x0004 0x0002 0x0001 0x807f Meaning Test finished Unused Mux test succeeded Good I RAM Good Y RAM Good X RAM Good I ROM Good Y ROM Good X ROM All ok Memory tests overwrite the current contents of the RAM memories. 7.8.4 SCI Test Sci test is initialized with the 8-byte sequence 0x53 0x70 0xEE n 0 0 0 0, where n - 48 is the register number to test. The content of the given register is read and copied to SCI IN0. If the register to be tested is SCI IN0, the result is copied to SCI IN1. Example: if n is 48, contents of SCI register 0 (SCI MODE) is copied to SCI IN0. Version 1.01, 2007-09-03 44 VLSI Solution y VS1103B VS1103B 8. VS1103B REGISTERS 8 8.1 VS1103B Registers Who Needs to Read This Chapter User software is required when a user wishes to add some own functionality like DSP effects to VS1103B. However, most users of VS1103B don't need to worry about writing their own code, or about this chapter, including those who only download software plugins from VLSI Solution's Web site. 8.2 The Processor Core VS DSP is a 16/32-bit DSP processor core that also had extensive all-purpose processor features. VLSI Solution's free VSKIT Software Package contains all the tools and documentation needed to write, simulate and debug Assembly Language or Extended ANSI C programs for the VS DSP processor core. VLSI Solution also offers a full Integrated Development Environment VSIDE for full debug capabilities. 8.3 VS1103B Memory Map VS1103B's Memory Map is shown in Figure 14. 8.4 SCI Registers SCI registers described in Chapter 6.6 can be found here between 0xC000..0xC00F. In addition to these registers, there is one in address 0xC010, called SCI CHANGE. SCI registers, prefix SCI Abbrev[bits] Description CHANGE[5:0] Last SCI access address. SCI CHANGE bits Bits Description 4 1 if last access was a write cycle. 3:0 SPI address of last access. Reg 0xC010 Type r Reset 0 Name SCI CH WRITE SCI CH ADDR 8.5 Serial Data Registers SDI registers, prefix SER Abbrev[bits] Description DATA Last received 2 bytes, big-endian. DREQ[0] DREQ pin control. Reg 0xC011 0xC012 Type r w Reset 0 0 Version 1.01, 2007-09-03 45 VLSI Solution y VS1103B VS1103B 8. VS1103B REGISTERS Instruction (32-bit) X (16-bit) Y (16-bit) 0000 0030 0500 System Vectors User Instruction RAM X DATA RAM Y DATA RAM 0000 0030 0500 1800 1880 1940 User Space Stack User Space Stack 1800 1880 1940 1C00 1E00 4000 1C00 1E00 4000 Instruction ROM 8000 X DATA ROM Y DATA ROM 8000 C000 Hardware Register Space C000 C100 C100 Figure 14: User's Memory Map. 8.6 DAC Registers DAC registers, prefix DAC Abbrev[bits] Description FCTLL DAC frequency control, 16 LSbs. FCTLH DAC frequency control 4MSbs, PLL control. LEFT DAC left channel PCM value. RIGHT DAC right channel PCM value. Reg 0xC013 0xC014 0xC015 0xC016 Type rw rw rw rw Reset 0 0 0 0 Every fourth clock cycle, an internal 26-bit counter is added to by (DAC FCTLH & 15) x 65536 + DAC FCTLL. Whenever this counter overflows, values from DAC LEFT and DAC RIGHT are read and a DAC interrupt is generated. Version 1.01, 2007-09-03 46 VLSI Solution y VS1103B VS1103B 8. VS1103B REGISTERS 8.7 GPIO Registers GPIO registers, prefix GPIO Abbrev[bits] Description DDR[3:0] Direction. IDATA[3:0] Values read from the pins. ODATA[3:0] Values set to the pins. Reg 0xC017 0xC018 0xC019 Type rw r rw Reset 0 0 0 GPIO DIR is used to set the direction of the GPIO pins. 1 means output. GPIO ODATA remembers its values even if a GPIO DIR bit is set to input. GPIO registers don't generate interrupts. Note that in VS1103B the VSDSP registers can be read and written through the SCI WRAMADDR and SCI WRAM registers. You can thus use the GPIO pins quite conveniently. Version 1.01, 2007-09-03 47 VLSI Solution y VS1103B VS1103B 8. VS1103B REGISTERS 8.8 Interrupt Registers Interrupt registers, prefix INT Abbrev[bits] Description ENABLE[7:0] Interrupt enable. GLOB DIS[-] Write to add to interrupt counter. GLOB ENA[-] Write to subtract from interript counter. COUNTER[4:0] Interrupt counter. Reg 0xC01A 0xC01B 0xC01C 0xC01D Type rw w w rw Reset 0 0 0 0 INT ENABLE controls the interrupts. The control bits are as follows: INT ENABLE bits Description Enable Timer 1 interrupt. Enable Timer 0 interrupt. Enable UART RX interrupt. Enable UART TX interrupt. Enable AD modulator interrupt. Enable Data interrupt. Enable SCI interrupt. Enable DAC interrupt. Name INT EN INT EN INT EN INT EN INT EN INT EN INT EN INT EN TIM1 TIM0 RX TX MODU SDI SCI DAC Bits 7 6 5 4 3 2 1 0 Note: It may take upto 6 clock cycles before changing INT ENABLE has any effect. Writing any value to INT GLOB DIS adds one to the interrupt counter INT COUNTER and effectively disables all interrupts. It may take upto 6 clock cycles before writing to this register has any effect. Writing any value to INT GLOB ENA subtracts one from the interrupt counter (unless INT COUNTER already was 0). If the interrupt counter becomes zero, interrupts selected with INT ENABLE are restored. An interrupt routine should always write to this register as the last thing it does, because interrupts automatically add one to the interrupt counter, but subtracting it back to its initial value is the responsibility of the user. It may take upto 6 clock cycles before writing this register has any effect. By reading INT COUNTER the user may check if the interrupt counter is correct or not. If the register is not 0, interrupts are disabled. Version 1.01, 2007-09-03 48 VLSI Solution y VS1103B VS1103B 8. VS1103B REGISTERS 8.9 A/D Modulator Registers Interrupt registers, prefix AD Abbrev[bits] Description DIV A/D Modulator divider. DATA A/D Modulator data. AD DIV bits Description 1 in powerdown. Divider. Reg 0xC01E 0xC01F Type rw rw Reset 0 0 Name ADM POWERDOWN ADM DIVIDER Bits 15 14:0 ADM DIVIDER controls the AD converter's sampling frequency. To gather one sample, 128 x n clock cycles are used (n is value of AD DIV). The lowest usable value is 4, which gives a 48 kHz sample rate when CLKI is 24.576 MHz. When ADM POWERDOWN is 1, the A/D converter is turned off. AD DATA contains the latest decoded A/D value. Version 1.01, 2007-09-03 49 VLSI Solution y VS1103B Watchdog v1.0 2002-08-26 VS1103B 8. VS1103B REGISTERS 8.10 The watchdog consist of a watchdog counter and some logic. After reset, the watchdog is inactive. The counter reload value can be set by writing to WDOG CONFIG. The watchdog is activated by writing 0x4ea9 to register WDOG RESET. Every time this is done, the watchdog counter is reset. Every 65536'th clock cycle the counter is decremented by one. If the counter underflows, it will activate vsdsp's internal reset sequence. Thus, after the first 0x4ea9 write to WDOG RESET, subsequent writes to the same register with the same value must be made no less than every 65536xWDOG CONFIG clock cycles. Once started, the watchdog cannot be turned off. Also, a write to WDOG CONFIG doesn't change the counter reload value. After watchdog has been activated, any read/write operation from/to WDOG CONFIG or WDOG DUMMY will invalidate the next write operation to WDOG RESET. This will prevent runaway loops from resetting the counter, even if they do happen to write the correct number. Writing a wrong value to WDOG RESET will also invalidate the next write to WDOG RESET. Reads from watchdog registers return undefined values. 8.10.1 Registers Watchdog, prefix WDOG Type Reset Abbrev Description w 0 CONFIG Configuration w 0 RESET Clock configuration w 0 DUMMY[-] Dummy register Reg 0xC020 0xC021 0xC022 Version 1.01, 2007-09-03 50 VLSI Solution y VS1103B UART v1.0 2002-04-23 VS1103B 8. VS1103B REGISTERS 8.11 RS232 UART implements a serial interface using rs232 standard. Start bit D0 D1 D2 D3 D4 D5 D6 Stop D7 bit Figure 15: RS232 Serial Interface Protocol When the line is idling, it stays in logic high state. When a byte is transmitted, the transmission begins with a start bit (logic zero) and continues with data bits (LSB first) and ends up with a stop bit (logic high). 10 bits are sent for each 8-bit byte frame. 8.11.1 Registers UART registers, prefix UARTx Type Reset Abbrev Description r 0 STATUS[3:0] Status r/w 0 DATA[7:0] Data r/w 0 DATAH[15:8] Data High r/w 0 DIV Divider Reg 0xC028 0xC029 0xC02A 0xC02B 8.11.2 Status UARTx STATUS A read from the status register returns the transmitter and receiver states. UARTx STATUS Bits Bits Description 3 Receiver overrun 2 Receiver data register full 1 Transmitter data register full 0 Transmitter running Name UART UART UART UART ST ST ST ST RXORUN RXFULL TXFULL TXRUNNING UART ST RXORUN is set if a received byte overwrites unread data when it is transferred from the receiver shift register to the data register, otherwise it is cleared. UART ST RXFULL is set if there is unread data in the data register. UART ST TXFULL is set if a write to the data register is not allowed (data register full). UART ST TXRUNNING is set if the transmitter shift register is in operation. Version 1.01, 2007-09-03 51 VLSI Solution y VS1103B Data UARTx DATA VS1103B 8. VS1103B REGISTERS 8.11.3 A read from UARTx DATA returns the received byte in bits 7:0, bits 15:8 are returned as '0'. If there is no more data to be read, the receiver data register full indicator will be cleared. A receive interrupt will be generated when a byte is moved from the receiver shift register to the receiver data register. A write to UARTx DATA sets a byte for transmission. The data is taken from bits 7:0, other bits in the written value are ignored. If the transmitter is idle, the byte is immediately moved to the transmitter shift register, a transmit interrupt request is generated, and transmission is started. If the transmitter is busy, the UART ST TXFULL will be set and the byte remains in the transmitter data register until the previous byte has been sent and transmission can proceed. 8.11.4 Data High UARTx DATAH The same as UARTx DATA, except that bits 15:8 are used. 8.11.5 Divider UARTx DIV UARTx DIV Bits Bits Description 15:8 Divider 1 (0..255) 7:0 Divider 2 (6..255) Name UART DIV D1 UART DIV D2 The divider is set to 0x0000 in reset. The ROM boot code must initialize it correctly depending on the master clock frequency to get the correct bit speed. The second divider (D2 ) must be from 6 to 255. The communication speed f = TX/RX speed in bps. fm (D1 +1)x(D2 ) , where fm is the master clock frequency, and f is the Divider values for common communication speeds at 26 MHz master clock: Example UART Speeds, fm = 26M Hz Comm. Speed [bps] UART DIV D1 UART DIV D2 4800 85 63 9600 42 63 14400 42 42 19200 51 26 28800 42 21 38400 25 26 57600 1 226 115200 0 226 Version 1.01, 2007-09-03 52 VLSI Solution y VS1103B Interrupts and Operation VS1103B 8. VS1103B REGISTERS 8.11.6 Transmitter operates as follows: After an 8-bit word is written to the transmit data register it will be transmitted instantly if the transmitter is not busy transmitting the previous byte. When the transmission begins a TX INTR interrupt will be sent. Status bit [1] informs the transmitter data register empty (or full state) and bit [0] informs the transmitter (shift register) empty state. A new word must not be written to transmitter data register if it is not empty (bit [1] = '0'). The transmitter data register will be empty as soon as it is shifted to transmitter and the transmission is begun. It is safe to write a new word to transmitter data register every time a transmit interrupt is generated. Receiver operates as follows: It samples the RX signal line and if it detects a high to low transition, a start bit is found. After this it samples each 8 bit at the middle of the bit time (using a constant timer), and fills the receiver (shift register) LSB first. Finally if a stop bit (logic high) is detected the data in the receiver is moved to the reveive data register and the RX INTR interrupt is sent and a status bit[2] (receive data register full) is set, and status bit[2] old state is copied to bit[3] (receive data overrun). After that the receiver returns to idle state to wait for a new start bit. Status bit[2] is zeroed when the receiver data register is read. RS232 communication speed is set using two clock dividers. The base clock is the processor master clock. Bits 15-8 in these registers are for first divider and bits 7-0 for second divider. RX sample frequency is the clock frequency that is input for the second divider. Version 1.01, 2007-09-03 53 VLSI Solution y VS1103B Timers v1.0 2002-04-23 VS1103B 8. VS1103B REGISTERS 8.12 There are two 32-bit timers that can be initialized and enabled independently of each other. If enabled, a timer initializes to its start value, written by a processor, and starts decrementing every clock cycle. When the value goes past zero, an interrupt is sent, and the timer initializes to the value in its start value register, and continues downcounting. A timer stays in that loop as long as it is enabled. A timer has a 32-bit timer register for down counting and a 32-bit TIMER1 LH register for holding the timer start value written by the processor. Timers have also a 2-bit TIMER ENA register. Each timer is enabled (1) or disabled (0) by a corresponding bit of the enable register. 8.12.1 Registers Timer registers, prefix TIMER Type Reset Abbrev Description r/w 0 CONFIG[7:0] Timer configuration r/w 0 ENABLE[1:0] Timer enable r/w 0 T0L Timer0 startvalue - LSBs r/w 0 T0H Timer0 startvalue - MSBs r/w 0 T0CNTL Timer0 counter - LSBs r/w 0 T0CNTH Timer0 counter - MSBs r/w 0 T1L Timer1 startvalue - LSBs r/w 0 T1H Timer1 startvalue - MSBs r/w 0 T1CNTL Timer1 counter - LSBs r/w 0 T1CNTH Timer1 counter - MSBs Reg 0xC030 0xC031 0xC034 0xC035 0xC036 0xC037 0xC038 0xC039 0xC03A 0xC03B 8.12.2 Configuration TIMER CONFIG TIMER CONFIG Bits Bits Description 7:0 Master clock divider Name TIMER CF CLKDIV TIMER CF CLKDIV is the master clock divider for all timer clocks. The generated internal clock fm frequency fi = c+1 , where fm is the master clock frequency and c is TIMER CF CLKDIV. Example: With a 12 MHz master clock, TIMER CF DIV=3 divides the master clock by 4, and the output/sampling clock would thus be fi = 12M Hz = 3M Hz. 3+1 Version 1.01, 2007-09-03 54 VLSI Solution y VS1103B Configuration TIMER ENABLE TIMER ENABLE Bits Bits Description 1 Enable timer 1 0 Enable timer 0 VS1103B 8. VS1103B REGISTERS 8.12.3 Name TIMER EN T1 TIMER EN T0 8.12.4 Timer X Startvalue TIMER Tx[L/H] The 32-bit start value TIMER Tx[L/H] sets the initial counter value when the timer is reset. The timer fi interrupt frequency ft = c+1 where fi is the master clock obtained with the clock divider (see Chapter 8.12.2 and c is TIMER Tx[L/H]. Example: With a 12 MHz master clock and with TIMER CF CLKDIV=3, the master clock fi = 3M Hz. If TIMER TH=0, TIMER TL=99, then the timer interrupt frequency ft = 3M Hz = 30kHz. 99+1 8.12.5 Timer X Counter TIMER TxCNT[L/H] TIMER TxCNT[L/H] contains the current counter values. By reading this register pair, the user may get knowledge of how long it will take before the next timer interrupt. Also, by writing to this register, a one-shot different length timer interrupt delay may be realized. 8.12.6 Interrupts Each timer has its own interrupt, which is asserted when the timer counter underflows. Version 1.01, 2007-09-03 55 VLSI Solution y VS1103B System Vector Tags VS1103B 8. VS1103B REGISTERS 8.13 The System Vector Tags are tags that may be replaced by the user to take control over several decoder functions. 8.13.1 AudioInt, 0x20 Normally contains the following VS DSP assembly code: jmpi DAC_INT_ADDRESS,(i6)+1 The user may, at will, replace the first instruction with a jmpi command to gain control over the audio interrupt. 8.13.2 SciInt, 0x21 Normally contains the following VS DSP assembly code: jmpi SCI_INT_ADDRESS,(i6)+1 The user may, at will, replace the instruction with a jmpi command to gain control over the SCI interrupt. 8.13.3 DataInt, 0x22 Normally contains the following VS DSP assembly code: jmpi SDI_INT_ADDRESS,(i6)+1 The user may, at will, replace the instruction with a jmpi command to gain control over the SDI interrupt. 8.13.4 ModuInt, 0x23 Normally contains the following VS DSP assembly code: jmpi MODU_INT_ADDRESS,(i6)+1 The user may, at will, replace the instruction with a jmpi command to gain control over the AD Modulator interrupt. Version 1.01, 2007-09-03 56 VLSI Solution y VS1103B TxInt, 0x24 VS1103B 8. VS1103B REGISTERS 8.13.5 Normally contains the following VS DSP assembly code: jmpi EMPTY_INT_ADDRESS,(i6)+1 The user may, at will, replace the instruction with a jmpi command to gain control over the UART TX interrupt. 8.13.6 RxInt, 0x25 Normally contains the following VS DSP assembly code: jmpi RX_INT_ADDRESS,(i6)+1 The user may, at will, replace the first instruction with a jmpi command to gain control over the UART RX interrupt. 8.13.7 Timer0Int, 0x26 Normally contains the following VS DSP assembly code: jmpi EMPTY_INT_ADDRESS,(i6)+1 The user may, at will, replace the first instruction with a jmpi command to gain control over the Timer 0 interrupt. 8.13.8 Timer1Int, 0x27 Normally contains the following VS DSP assembly code: jmpi EMPTY_INT_ADDRESS,(i6)+1 The user may, at will, replace the first instruction with a jmpi command to gain control over the Timer 1 interrupt. Version 1.01, 2007-09-03 57 VLSI Solution y VS1103B UserCodec, 0x0 VS1103B 8. VS1103B REGISTERS 8.13.9 Normally contains the following VS DSP assembly code: jr nop If the user wants to take control away from the standard decoder, the first instruction should be replaced with an appropriate j command to user's own code. The system usually activates the user program in less than 1 ms. After this, the user should steal interrupt vectors from the system, and insert user programs. 8.14 System Vector Functions The System Vector Functions are pointers to some functions that the user may call to help implementing his own applications. 8.14.1 WriteIRam(), 0x2 VS DSP C prototype: void WriteIRam(register i0 u int16 *addr, register a1 u int16 msW, register a0 u int16 lsW); This is the preferred way to write to the User Instruction RAM. 8.14.2 ReadIRam(), 0x4 VS DSP C prototype: u int32 ReadIRam(register i0 u int16 *addr); This is the preferred way to read from the User Instruction RAM. A1 contains the MSBs and a0 the LSBs of the result. 8.14.3 DataBytes(), 0x6 VS DSP C prototype: u int16 DataBytes(void); Version 1.01, 2007-09-03 58 VLSI Solution y VS1103B VS1103B 8. VS1103B REGISTERS If the user has taken over the normal operation of the system by switching the pointer in UserCodec to point to his own code, he may read data from the Data Interface through this and the following two functions. This function returns the number of data bytes that can be read. 8.14.4 GetDataByte(), 0x8 VS DSP C prototype: u int16 GetDataByte(void); Reads and returns one data byte from the Data Interface. This function will wait until there is enough data in the input buffer. 8.14.5 GetDataWords(), 0xa VS DSP C prototype: void GetDataWords(register i0 y u int16 *d, register a0 u int16 n); Read n data byte pairs and copy them in big-endian format (first byte to MSBs) to d. This function will wait until there is enough data in the input buffer. 8.14.6 Reboot(), 0xc VS DSP C prototype: void Reboot(void); Causes a software reboot, i.e. jump to the standard firmware without reinitializing the IRAM vectors. This is NOT the same as the software reset function, which causes complete initialization. Version 1.01, 2007-09-03 59 VLSI Solution y VS1103B VS1103B 9. DOCUMENT VERSION CHANGES 9 Document Version Changes This chapter describes the most important changes to this document. Version 1.01 for VS1103B, 2007-09-03 * Corrected recording examples, Chapters 7.4.2 and 7.4.6. Version 1.00 for VS1103B, 2007-08-22 * Removed preliminary status. Version 0.4 for VS1103B, 2007-07-06 * Added SCI Multiple Write mode, Chapter 5.5.4. * Corrected documentation for SCI IN1 in Chapter 6.6.9. * Added note to always run a software reset after setting SCI CLOCKF to Chapter 6.6.4. Version 0.3 for VS1103B, 2007-04-24 * Added Buffer 1 and 2 sizes. Now both are 1 KiB (Chapter 6.3). * Size of ADPCM encode Buffer 3 increased to 1 KiB (Chapter 6.3.1). * Writing to SM ICONF also causes a software reset (Chapter 6.6.1). * SCI MODE's SS VER is now documented as 7 for VS1103 (Chapter 6.6.2). * New register bit SARC DREQ512 (Chapter 6.6.13). Version 0.2 for VS1103a, 2007-01-29 * Minor modifications. Version 0.1 for VS1103a, 2007-01-11 * First release. Version 1.01, 2007-09-03 60 VLSI Solution y VS1103B 10 Contact Information VLSI Solution Oy Entrance G, 2nd floor Hermiankatu 8 FIN-33720 Tampere FINLAND Fax: +358-3-3140-8288 Phone: +358-3-3140-8200 Email: sales@vlsi.fi URL: http://www.vlsi.fi/ VS1103B 10. CONTACT INFORMATION Version 1.01, 2007-09-03 61 |
Price & Availability of VS1103B
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |